module dmem_test#(parameter A_WIDTH = 13, D_WIDTH = 34, INSTR_WIDTH = 136);

	reg  reset;
	reg  clk;
	reg  read_write_req;
	reg  write_en;
	reg  [A_WIDTH-1 : 0] addr;
	reg  [D_WIDTH-1 : 0] din;
	wire [INSTR_WIDTH-1 : 0] dout;
	wire refused;
	
	dmem dut
	(
		.reset_i(reset)
		,.clk(clk)
		,.read_write_req_i(read_write_req)
		,.write_en_i(write_en)
		,.addr_i(addr)
		,.din_i(din)
		,.dout_o(dout)
		,.refused_o(refused)
	);
	
	//Toggle every 10 ns
	initial
		begin
			clk = 0;
			forever #10 clk = !clk;
		end
		
	initial
		begin
			// 200ns
			// Reset the memory
			#200
			reset <= 1'b1;
			// 220ns
			// Unassert reset
			#20
			reset <= 1'b0;
			// 220ns
			// Write 1 into address 0
			#20
			read_write_req = 1'b1;
			write_en = 1'b1;
			addr = 10'b0;
			din = 34'b1;
			// 240ns
			// Write 2 into address 1
			#20
			addr = 10'b1;
			din = 34'b10;
			// 260ns
			// Write 3 into address 2
			#20
			addr = 10'b10;
			din = 34'b11;
			// 280ns
			// Write 4 into address 3
			#20
			addr = 10'b11;
			din = 34'b100;
			// 300ns
			// Read back addresses
			#20
			write_en = 1'b0;
			addr = 10'b0;
			din = 34'b0;			
		end
	
	

endmodule
